A content addressable memory including capacitor memory cell

ABSTRACT

A content addressable memory is realized, wherein capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line. The plate of capacitor couples to second terminal, but it does not couple to first, third and fourth terminal. With no coupling, the plate can swing ground to high level, which can realize to remove internal negative voltage for memory operation and by turning off word line during standby no holding current is required to sustain data. In this manner, active current is dramatically reduced and standby current is only leakage current. The match line has compare circuits which include series MOS transistors for each memory cell, wherein the storage node is connected to the gate of first MOS transistor, and the comparand data is connected to the gate of second MOS transistor. Hidden refresh is asserted during precharge of match operation. The size of CAM is smaller than that of SRAM, DRAM-based CAM, and the height of cell is almost same as that of control circuit.

FIELD OF INVENTION

The invention relates to content addressable memory (CAM), and moreparticularly to CAM including capacitor memory cell which stores data ina capacitor.

BACKGROUND

A content addressable memory (CAM) device is a storage device that isparticularly suitable for matching functions because it can beinstructed to compare a specific pattern of comparand data with datastored in an associative CAM array. A CAM can include a number of datastorage locations, each of which can be accessed by a correspondingaddress. Functionality of a CAM depends at least in part on whether theCAM includes binary or ternary CAM cells.

Typical binary CAM cells are able to store to states of information, alogic one state and a logic zero state. Binary CAM cells typicallyinclude a memory cell and a compare circuit. The compare circuitcompares the comparand data with data stored in the memory cell andprovides the match result to a match line. Columns of binary CAM cellsmay be globally masked by mask data stored in one or more global maskregisters.

Ternary CAM cells are mask-per-bit CAM cells that effectively storethree states of information, namely a logic one state, a logic zerostate, and a don't care state for compare operations. Ternary CAM cellstypically include a second memory cell that stores local mask data forthe each ternary CAM cell. The local mask data masks the comparisonresult of the comparand data with the data stored in the first memorycell such that, when the mask bit has a first predetermined value (alogic low, for example) its compare operation will be masked so that thecomparison result does not affect the match line. The ternary CAM celloffers more flexibility to the user to determine on an entry-per-entrybasis which bits in a word will be masked during a compare operation.

In FIG. 1, a prior art of SRAM-based CAM cell is depicted. It is one ofthe conventional CAM devices which use a static random access memory(SRAM) device. CAM cell 110 and 110′ include two SRAM cells 120 and120′. CAM cell offers ternary data storage. Preferably, these two SRAMcells 120 and 120′ together can store up to four different states. Threeof these four states (“0”, “1”, and “X”) are used in CAM cell, makingCAM cell into a ternary state CAM cell. Each of SRAM cells 120 and 120′includes two inverter latches, 111 and 112, 111′ and 112′ to store data.The stored data in two cells are inverted when those are written throughthe access transistor 113, 114, 113′ and 114′ from the memory controlcircuit, such that the bit line 115 and the inverting bit line 116 are apair to store one data into latch 111 and 112, the bit line 115′ and theinverting bit line 116′ are a pair to store another data into latch 111′and 112′, the bit line 115 and 115′ are inverted from the controlcircuit. As a result, the output of inverter 111 and the output ofinverter 111′ are inverted to achieve compare operation when comparanddata are asserted.

Compare circuit 123 and 123′ compare the data stored in the memory cell120 and 120′ with comparand data provided on compare signal lines 117and 117′. Compare circuit 123 includes transistors 118 and 119 todischarge the match line 122 when both transistors are turned on.Compare circuit 123′ includes transistors 118′ and 119′ to discharge thematch line 122 when both transistors are turned on. Transistors 118 and119 are coupled in series to form a first path of the compare circuit123, and transistors 118′ and 119′ are coupled in series to form asecond path of the compare circuit 123′. The sources (drains) oftransistors 118 and 118′ are coupled to the match line, while the drains(sources) of transistors 119 and 119′ are coupled to ground potential.These n-channel series devices perform the comparison function.

Regarding control inputs to each of the transistors 118, 119, 118′ and119′, the gates of transistors 118 and 118′ are coupled to receive datafrom the first cell 120 and second cell 120′, respectively. The gate oftransistor 119 receives comparand data from compare signal line 117 andthe gate of transistor 119′ receives comparand data from compare signalline 117′. The sources (drains) of transistors 118 and 118′ are coupledto the match line. Compare circuit 123 and 123′ pull the pre-chargedmatch line to a logic zero state when the comparand data does not match(i.e., mismatches) the data stored in the memory cell 110 and 110′. Tomask compare operation, comparand 117 and 117′ have logic value “low”for both lines, which makes match line to keep pre-charged voltage. Thismakes match (i.e., matches). SRAM-based CAM has very good performancefor storing data and comparing match line, but 6 transistor-based SRAMhas relatively large die area and high subthreshold leakage current forwhole chip even though single memory cell has very little leakage.

In FIG. 2, a prior art of DRAM based CAM is illustrated, U.S. Pat. No.6,331,961, wherein CAM cell 230 and 230′ include two DRAM cells 240 and240′. CAM cell offers ternary data storage. Preferably, these two DRAMcells 240 and 240′ together can store up to four different states. Threeof these four states (“0”, “1”, and “X”) are used in CAM cell, makingCAM cell into a ternary state CAM cell. Each of SRAM cells 240 and 240′includes storage capacitor to store data. The stored data in two cellsare inverted when those are written through the access transistor 232,233, 232′ and 233′ from the memory control circuit, such that the bitline 234 drives to store one data into the storage capacitor 231, thebit line 234′ drives to store another data into the storage capacitor231′, the bit line 234 and 234′ are inverted from the control circuit.As a result, the stored data of capacitor 231 and 231′ are inverted toachieve compare operation.

Compare circuit 241 and 241′ compare the data stored in the memory cell230 and 230′ with comparand data provided on compare signal lines 236and 236′. Compare circuit 241 includes transistors 237 and 238 todischarge the match line 242 when both transistors are turned on.Compare circuit 241′ includes transistors 237′ and 238′ to discharge thematch line 242 when both transistors are turned on. Transistors 237 and238 are coupled in series to form a first path of the compare circuit241, and transistors 237′ and 238′ are coupled in series to form asecond path of the compare circuit 241′. The sources (drains) oftransistors 237 and 237′ are coupled to the match line, while the drains(sources) of transistors 238 and 238′ are coupled to ground potential.These n-channel series devices perform the comparison function.

However, DRAM requires multiple internal voltage, such that word linehas VPP which is higher than that of bit line high level, the pre-chargelevel of bit line has half VDD (VDD is array voltage), the capacitorplate has half VDD, and the bulk of the access transistor 232, 233, 232′and 233′ have negative voltage. And it is difficult to turn off NMOSdevice by the storage node because the storage node does not have fullhigh level or full low level because the capacitor will discharge.

Another memory device can be applied for configuring CAM cell. A RAMdevice based on said Negative Differential Resistance (NDR) device orso-called thyristor device, U.S. Pat. No. 6,229,161 “Semiconductorcapacitively-coupled negative differential resistance device and itsapplications in high-density high-speed memories and in power switches”,has been introduced. These NDR-based RAM devices typically include atleast two active elements, including an NDR device. The NDR device canbe any one of a variety of NDR devices ranging from a simple bipolartransistor to more complicated quantum-effect devices. The NDR-based RAMdevice supports a cell area smaller than conventional SRAM cells becauseof the smaller number of active devices and interconnections.

However, the NDR-based RAM cell stores data into the state of thethyristor which is on or off, therefore the holding current isrelatively high for whole chip during standby even though each cell hasvery little holding current to sustain the turn-on state of thyristorwhen the stored data is high. Moreover, it has high active powerconsumption as well, to generate negative voltage for switchinggate-like device, which is said second word line. The internal negativevoltage cuts off subthreshold current of the gate-like device to coupleNDR device. Without negative voltage for the second word line, thestored data will be lost by the subthreshold leakage through gate-likedevice.

Still, there is a need in the art for a content addressable memory,which realizes high density, low power and simple structure to fabricateon the wafer.

SUMMARY OF INVENTION

The present invention is directed to a content addressable memory (CAM)including capacitor memory cell. The invention does not use staticrandom access memory (SRAM) which has 6 transistor memory cell, ordynamic random access memory (DRAM) which stores data in a capacitorthrough MOS (Metal Oxide Semiconductor) access transistor havingsubthreshold leakage and multiple internal voltage generators, orNDR-based memory which requires holding current and internal negativevoltage generator.

Rather, the invention is drawn to a capacitor memory cell based CAMwhich stores data in a capacitor and a p-n-p-n diode controls to storeor read data “1” or “0”, wherein diode is only turned on during storingor reading data. There is no need of complex MOS device to implement thecapacitor memory cell. Diode need not be a high performance device norhave a high current gain. Moreover, capacitor memory does not requireinternal negative voltage generator for operation and area is smallerthan that of DRAM and SRAM based memory. And diode current is generallymuch higher than that of MOS transistor, which diode can drive bit linequickly and achieve memory speed fast. Capacitor memory based CAM offersthe advantages of capacitor memory without the speed penalty associatedwith refresh cycle. The present invention devotes a circuit including acapacitor memory cell to configure a CAM on the bulk of wafer and on theSOI wafer, and the height of cell is almost same as that of controlcircuit to integrate CAM cells and other control circuits on a chip, anda timing to refresh sustaining data for a predetermined time. In sodoing, the invention answers the need to take advantage of capacitormemory in a CAM while preserving the high speed performance demanded ofany CAM.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodimentswhich are illustrated in the various drawing figures.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention and togetherwith the description, serve to explain the principles of the invention:

FIG. 1 depicts an SRAM-based content addressable memory (CAM) cell as aprior art.

FIG. 2 depicts a DRAM-based content addressable memory (CAM) cell as aprior art.

FIG. 3 illustrates the present invention of capacitor memory based CAM.

FIG. 4 illustrates write and read timing of the capacitor memory shownin FIG. 3.

FIGS. 5 a and 5 b illustrate I-V curve of the capacitor memory shown inFIG. 3.

FIG. 6 provides a truth table summarizing the logical relationshipsamong various signals in FIG. 3.

FIG. 7 illustrates refresh operation for the present invention when thestored data is “high”.

FIG. 8 illustrates refresh operation for the present invention when thestored data is “low”.

FIGS. 9 a and 9 b illustrate the cross sectional views of one embodimentfor the present invention on the SOI wafer. 9 a is shown from the wordline direction, and 9 b is shown from the bit line direction.

FIGS. 10 a and 10 b illustrate the cross sectional views of onepartially vertical embodiment for the present invention on the bulk. 10a is shown from the word line direction, and 10 b is shown from the bitline direction.

FIG. 11 illustrates the cross sectional view of one vertical embodimentof the memory cell which is seen from the word line direction of the CAMfor the present invention on the SOI wafer.

FIG. 12 illustrates an alternative embodiment with reverse configurationfor the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)

Reference is made in detail to the preferred embodiments of the presentinvention, which is a content addressable memory (CAM) includingcapacitor memory cell. While the invention is described in conjunctionwith the preferred embodiments, the invention is not intended to belimited by these preferred embodiments. On the contrary, the inventionis intended to cover alternatives, modifications and equivalents, whichmay be included within the spirit and scope of the invention as definedby the appended claims. Furthermore, in the following detaileddescription of the invention, numerous specific details are set forth inorder to provide a thorough understanding of the invention. However, asis obvious to one ordinarily skilled in the art, the invention may bepracticed without these specific details. In other instances, well-knownmethods, procedures, components, and circuits have not been described indetail so that aspects of the invention will not be obscured.

In FIG. 3, a schematic of the CAM cell for the present invention isshown. The memory cell 310 and 310′ store data in storage capacitor 336and 336′. These capacitor 336 and 336′ should have enough capacitance toretain data for a required time, which can include trench capacitor orhigh dielectric capacitor. The plate of capacitor 336 and 336′ couple tostorage node 334 and 334′, but they have no coupling region to node 333,335, 333′ and 335′. Storage node 334 and 334′ serve as the bases ofn-p-n transistor 331 and 331′ respectively. The emitter 335 and 335′ ofn-p-n transistors are connected to word line 344, collector of n-p-n 331and 331′ serve as the cathodes of diode 332 and 332′ respectively. Theanode of diode 332 and 332′ serve as the bit line 339 and 339′respectively. PMOS pull-up 341 and 341′ sustain the turn-on state ofdiode for realizing nondestructive read. Node 342 and 342′ arebi-directional signal to read or write data. Compare circuit 320 and320′ share a match line 346 which includes series MOS transistors, 337,338, 337′ and 338′.

In FIG. 4, write and read timing are illustrated for the memory cell ofthe present invention. Word line 444 stays at high level during standby,and moves to ground level when writing or reading. Bit line 439 stays athigh level during standby. Then bit line 439 determines to store data“1” or data “0”. Write operation has a sequence to store data safely. Toprepare writing data “1” is to move word line 444 to ground level asshown 451 in FIG. 4, and then to raise plate signal 445, while bit line439 keeps high level but it will go down slightly by turn-on diode. Thenthe storage node 434 becomes forward bias (VF1) from word line which isat ground during write operation, and the floating node 433 which is thecathode of diode 432 becomes forward bias (VF2) from the bit line whichis at high level to write data “1”. The current flows from bit line toword line, after then plate returns to ground level, however risingplate can not couple storage node because current flow is stronger thancoupling. As a result, the storage node 434 keeps forward bias andp-n-p-n diode is still turned-on. After plate returned to ground level,the word line 444 returns to high level, which cut off the current pathfrom the bit line to word line because both lines are at high level andplate is isolated by insulator. After write cycle, reverse bias leakageof diode helps to keep data “1” because the storage node dischargestoward high level, which makes stronger forward bias for the storagenode 434, while the floating node 433 becomes strong reverse bias but ithas very small parasitic capacitance only, hence the floating node 433is controlled by the storage node 434 which has high capacitance. Inthis sense, data “1” does not need refresh cycle. However, data “1” canbe lost when reading data “1”, word line moves down and pulls down bitline while word line is low without pull-up device with multiple readcycles before refresh cycle. To keep data “1”, PMOS pull-up is connectedto bit line 439 and keeps turn-on state, and realizes non destructiveread which removes restoring procedure and reduces cycle time.

To write data “0”, a sequence clears the state of diode before writingto have the same stored level regardless of previous stored level, whichstored level can be discharged after a long time. This sequence needs toturn-on diode first as shown 452 in FIG. 4. After turn-on diode, bitline 439 goes down to ground level and turns off diode because word lineand bit line are at ground level. After then, plate 445 returns toground level which plate couples to storage node 434 to lower level thanthat of ground level, because the storage node 434 is floating. Storedvoltage of data “0” is determined by the swing voltage of plate and thecapacitance of storage node. After then, storage node 434 will bedischarged by reverse bias leakage toward the adjacent nodes which stayat high level during standby or unselected. Capacitor oxide leakagewould be ignorable in most applications with thick oxide or low leakageinsulator. The floating node 433 is third terminal which is the cathodeof diode 432 in FIG. 3, which node 433 depends on the state of the n-p-ntransistor (331 in FIG. 3) because the third terminal 433 has very smallparasitic capacitance and floating, while storage node has more chargesto sustain the voltage which is stored data. The inverting voltageoutput is appeared in the bit line 439 and non-inverting current output453 is appeared in the bit line. Refresh cycles are periodicallyasserted to sustain data “0”, which operation includes to read voltagefrom the cell and write inverting voltage to the cell.

In the present invention, memory array can use single power supply asshown in FIG. 4. This is very useful to configure high density and highspeed memory. In some applications, plate will swing from ground levelto slightly higher voltage than that of word line, which plate pullsdown storage node lower to retain data longer. Plate voltage can beinternally generated or externally supplied. This is another usefulscheme to configure memory array.

In FIGS. 5 a and 5 b in view of FIG. 3, I-V curves are shown for thecapacitor memory cell of the present invention. During standby, wordline voltage (Vwl) is at high level which does not make any currentexcept oxide leakage. When reading data “1”, word line moves to groundlevel and makes current flow (Iwl) through bit line in FIG. 5 a. Thismeans that the storage node is forward biased from the word line. Thefloating node 333 in FIG. 3 moves quickly down by the forward biasedn-p-n 331 in FIG. 3, where the floating node 333 is floating and hasvery low parasitic capacitance. When reading data “0”, the storage node334 stays at lower than ground level, which makes reverse bias for n-p-ntransistor, hence n-p-n transistor can not flow current, and then p-ndiode 332 can not flow current either. Voltage output of bit line ishigh level, which makes inverting voltage output to bit line. Andnon-inverting current output (IDD) 453 in FIG. 4 is appeared in the bitline. FIG. 5 b illustrates reading data ‘0’ which has no current, thatis, turned-off diode. And forward blocking voltage (Vfb) is illustratedwhen storing data “0”, where forward blocking voltage is determined bythe plate swing level and storage capacitance.

In FIG. 6 in view of FIG. 3, a truth table T20 is shown summarizing thebehavior of CAM cell in relation to signal states maintained by variouselements within CAM cell in accordance with the present invention. Firstcolumn T21 lists binary states of “0” and “1” that can be stored instorage node of the capacitor memory cell 310 in FIG. 3; second columnT22 lists binary states of “0” and “1” that can be stored in storagenode of the capacitor memory cell 310′ in FIG. 3. Third column T23 liststhe ternary states that can be maintained in one of the complementcompare data lines, namely cdata which is the signal 343′ in FIG. 3.Fourth column T24 lists the ternary states that can be maintained in theother complement compare data line, namely ncdata which is the signal343 in FIG. 3. Fifth column T25 lists “high” and “low” as the twoavailable voltage levels for match line 346. Finally, sixth column T26lists “match” and “mismatch” as the two possible results for comparingstates of ncdata line 343 and cdata line 343′ with the states of CAMcell.

Continuing with FIG. 6 in view of FIG. 3, row T31 indicates masked casewhere sdata and nsdata are “0”, which makes match line to stay thepre-charge level, regardless of the compare data because sdata andnsdata turn off MOS transistor 337 and 337′, rows T32-T33 both indicatethat “0” state of CAM cell is represented by “0” of capacitor memorycell 310, and “1” of capacitor memory cell 310′. In row T32, becausestate “1” of cdata line 343′ does not match state “0” of CAM cell, matchline 346 is driven “low” to indicate a partial mismatch of the data keyand the stored value (state “0”) of CAM cell. In row T33, because state“0” of cdata line 343′ matches state “0” of CAM cell, match line 346 isdriven “high” to indicate a partial match of the comparand and thestored value (state “0”) of CAM.

Continuing still with FIG. 6 in view of FIG. 3, rows T34-T35 bothindicate that “1” state of CAM cell is represented by “1” of capacitormemory cell 310 and “0” of capacitor cell 310′. In row T34, becausestate “1” of cdata line 343′ matches state “1” of CAM cell, match line346 is driven “high” to indicate a partial match of the comparand andthe stored value (state “1”) of CAM cell. In row T35, because state “0”of cdata line 343′ does not match state “1” of CAM cell, match line 346is driven “low” to indicate a partial mismatch of the comparand and thestored value (state “1”) of CAM cell.

Referring now to FIG. 7 in view of FIG. 3, a timing diagram for matchand refresh “1” operation is shown in accordance with one embodiment ofthe invention. As shown, for the match/compare operation the storagenode voltage 734 has enough voltage to turn on MOS device (337 in FIG.3) when stored data is “1”, which is forward bias voltage (VF) and nearthe high level. Match line 746 is pre-charged at the end of the fallingedge of the match line. This pre-charge makes match line 746 ready forthe following cycle. After the match operation, the result of match line746 is latched during pre-charge. Also effectively in the pre-charge ofmatch operation, word line 744 is turned on (active low), wherein thedata stored in capacitors (343 and 343′ in FIG. 3) are read,respectively, and saved into the sense amplifiers (not shown) throughbit line (339 and 339′ in FIG. 3). Sense amplifiers hold the data_true753 and data_bar 754 until the restore cycle 752 is completed. Inparticular, the restore cycle 752 performs to write the invertingvoltage data from sense amplifier into the bit line (339 and 339′ inFIG. 3), where data_bar 754 signal drives the bit line. It makes thecapacitor memory to recover the previous data from the read cycle 751.The plate 745 couples to storage node 734, however the plate 745 can notaffect the storage node 734, when the p-n-p-n diode is turned-on becausethe current flow is stronger than capacitive coupling. After refreshed,the stored data “1” will be discharged toward high level after, but thedischarge helps to sustain data “1”. In this sense, data “1” does notrequire refresh cycle while data “0” requires refresh cycle.

In FIG. 8, a timing diagram for match and refresh “0” operation is shownin accordance with one embodiment of the invention. The sense amplifierreads data from the cell, and has data_true 853 and data_bar 854 in thesense amplifier (not shown) during the read cycle 851. After compareoperation, diode is turned on by raising plate 845 in restore cycle 852in order to clear the storage node 834 which can be discharged from theprevious write or refresh cycle. After then, bit line 839 moves toground to turn off diode. After turning on diode, the plate 845 returnsfrom high level to ground level which couples to storage node 834 lowerthan ground level. After restoring, the storage node 834 will movetoward high level because word line 844 and bit line 839 are at highlevel during standby and unselected. Refresh will help to sustain data“0” effectively in the manner.

Continuing with FIG. 8 in view of FIG. 3, the refresh/restore operationcan be implemented in multiple stages in order to avoid speed penalty.Specifically, because restoring data can sometime take longer tocomplete (in the case of restoring a “0”), combining restore withrefresh slows down performance of the CAM. In FIGS. 7 and 8, refreshcycle has two separate cycles such that the first cycle is read and thesecond cycle is restore cycle. However, in slow applications, singlerefresh cycle is still available to reduce complexity of circuit controlbecause the capacitor memory is faster than conventional DRAM with usingdiode in order to read data from the storage node while DRAM needs towait the charge redistribution between the storage node and the bit linewhich has higher capacitance in general.

FIG. 9 a outlines one embodiment of a fabrication technique on the SOIwafer for the capacitor memory cell of the present invention (comparecircuit is not shown), wherein word line 911 is connected to n-typeregion 916 through silicide layer 915 which reduces contact resistance,n-type region 916 is attached to p-type region 917, p-type region 917 isattached to n-type region 918, n-type region 918 is attached to p-typeregion 919, p-type region 919 is attached to bit line 912 throughsilicide layer 920. The plate of capacitor 913 couples to p-type region917, which plate 913 has no coupling region to n-type region 916 andn-type region 918. Inversion layer 914 is isolated from the adjacentnodes, which inversion layer 914 can be appeared when the voltage ofplate 913 is higher than storage node 917. With no coupling region,plate can swing from ground level to high level because inversion layerdoes not make any leakage to adjacent nodes. The oxide layer betweenplate 913 and inversion layer 914 has higher dielectric constant thanthat of control circuit to have more capacitance, and the metal shuntingline 921 is added to connect to plate 913 repeatedly outside of thememory array to reduce resistance of polysilicon plate. The memory cellis isolated from the substrate region 924 by the isolation layer 923.The layer 922 blocks silicide. FIG. 9 b shows the bit line direction ofthe memory cell, where the cell is isolated from the substrate 924 byinsulator 923. The height of cell is almost same as control circuit.

This configuration removes complicated MOS device from the memory cell,as a result, the memory cell has a capacitor and a diode, which issimple to fabricate and analyze as long as reverse bias leakage andoxide leakage are controllable. Another leakage path is so-called backchannel effect in the planar structure of wafer from the parasitic MOStransistor, such that the substrate 924 serves as gate, n-type region916 and 918 serve as source/drain, p-type region 917 serves as body.Related references are disclosed, Chen et al, “Characterization ofback-channel subthreshold conduction of walled SOI devices”, IEEETransactions on electron Devices, Vol. 38, No. 12, pp 2722, December1991, and Shin et al, “Leakage current models of thin filmsilicon-on-insulator devices”, Applied Physics Letters, Vol. 72, No. 10,March 1998. This back channel effect is reduced or removed by addingadditional n-type ions near the bottom side of the third terminal 918,or applying high voltage (higher than the standby voltage of word line)to the substrate 924.

FIG. 10 a outlines one embodiment of a fabrication technique to removeback channel effect and add trench capacitor on the wafer for formingthe capacitor memory cell of the present invention wherein word line1011 is connected to n-type region 1016 through silicide layer 1015,n-type region 1016 is attached to p-type region 1017, p-type region 1017is attached to n-type region 1018, n-type region 1018 is attached top-type region 1019, p-type region 1019 is attached to bit line 1012through silicide layer 1020. To remove parasitic MOS transistor, p-typeregion 1019 is vertically attached on the n-type region 1018.Furthermore, in order to increase storage capacitance, trench capacitoris added as shown FIG. 10 b. This trench capacitor is formed between onestorage node and the other storage node after forming diode, such thatthe plate of trench capacitor 1014 is connected to plate 1013, and layer1014 and storage node 1017 are isolated by insulator and make capacitor.FIG. 10 b is shown from the bit line direction of the memory cell, wherethe whole memory cell is isolated from the well 1024 by insulator 1023.The height of cell is almost same as control circuit.

FIG. 11 outlines one vertical embodiment of a fabrication technique onthe bulk or SOI wafer for the capacitor memory cell, where the memorycell is implemented inside of trench area 1150, the plate 1156 is placedin the bottom, word line 1151 is connected to n-type region 1154 throughsilicide layer 1153, n-type region 1154 is attached to p-type region1155 which is on the lower side of region 1154 and is coupled by plate1156, p-type region 1155 is attached to n-type region 1157 which is onthe upper side of region 1155, n-type region 1157 is attached to p-typeregion 1158 which is on the upper side of region 1157, bit line 1152 isconnected to p-type region 1158. To make a p-n junction for region 1157and 1158, there is one of alternative embodiment, which is metalsemiconductor diode. The leakage of this diode between n-type 1157 andmetal 1158 does not matter for storing data because n-type region 1157is floating and does not have any data, where data is stored in theregion 1155. There is a related reference to fabricate metalsemiconductor diode with CMOS process, Sankaran et al, “Schottky barrierdiodes for millimeter wave detection in a foundry CMOS process”, IEEEElectron Device Letters, Vol. 26, No. 7, pp 492-494, July 2005. Thepresent invention can use various type of metal to form metalsemiconductor diode, and more useful applications are to use varioustypes of semiconductor, such as silicon, germanium, GaAs, SiGe andothers, as long as reverse bias leakage is controllable. The memory cellis isolated from the well or substrate region 1165 by insulator 1164.The control circuit is depicted in the same figure, such that the gate1160 has source/drain region 1161, another source/drain region 1163, andthe body 1162. This figure illustrates that the height of capacitormemory cell can be almost same as that of control circuit.

While the description here has been given for configuring the memorycircuit and structure, an alternative embodiment would work equally wellwith reverse connection. In FIG. 12, the word line 1244 is connected toemitter 1235, bit line 1239 is connected to cathode of diode 1232. Firstterminal 1235 is p-type and serves as word line, second terminal 1234 isn-type and serves as storage node, third terminal 1233 is p-type andfloating, and fourth terminal 1239 is n-type and serves as bit line.Plate 1245 couples to the storage node and has no coupling region withfirst, third and fourth terminal. NMOS pull-down 1241 is applied tosustain the turn-on state of diode when stored data is “1”. Node 1242 isbidirectional signal to write and read data. Word line and bit line stayat ground level, and plate stays at high level during standby.

CONCLUSION

A content addressable memory including capacitor memory cell is realizedon the bulk or SOI wafer. Fabrication is compatible with CMOS processwith additional steps. Memory cell area is minimized and smaller thanthat of DRAM, SRAM, or NDR-based CAM. There are many embodiments forimplementing the memory cells and circuits depending on theapplications.

Circuit implementation is simpler than that of these days memory havingmultiple power supply. The present invention has single or dual positivepower supply for the memory operation.

The refresh cycles are hidden from the outside of the chip, which canreduce the complexity of upper level system configuration.

The foregoing descriptions of specific embodiments of the invention havebeen presented for purposes of illustration and description. They arenot intended to be exhaustive or to limit the invention to the preciseforms disclosed. Obviously, many modifications and variations arepossible in light of the above teaching. The embodiments were chosen anddescribed in order to explain the principles and the application of theinvention, thereby enabling others skilled in the art to utilize theinvention in its various embodiments and modifications according to theparticular purpose contemplated. The scope of the invention is intendedto be defined by the claims appended hereto and their equivalents.

1. A content addressable memory, comprising: capacitor memory cellwherein includes a capacitor and a diode, which capacitor stores dataand diode controls to store data “1” or “0”, which diode has fourterminals, first terminal is n-type and serves as word line, secondterminal is p-type and serves as storage node, third terminal is n-typeand floating, fourth terminal is p-type and serves as bit line, andplate of capacitor couples to second terminal, which plate has nocoupling region to first, third and fourth terminal; and at least onecompare circuit coupled among the memory cell and at least one matchline to receive first and second signal sets and affect a logical stateof the match line in response to a predetermined logical relationshipbetween the first and second signal sets, the compare circuit includinga first transistor set and a second transistor set, wherein the firstsignal set couples to control a conduction state of the first transistorset and the second signal set couples to control a conduction state ofthe second transistor set, wherein the first signal set includes storeddata and the second signal set includes comparand data.
 2. The contentaddressable memory of claim 1, wherein can be implemented an alternativeembodiment with reverse configuration, such that diode has fourterminals, wherein first terminal is p-type and serves as word line,second terminal is n-type and serves as storage node, third terminal isp-type and floating, fourth terminal is n-type and serves as bit line,and plate of capacitor couples second terminal, which plate has nocoupling region to first, third and fourth terminal.
 3. (canceled) 4.(canceled)
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 8. (canceled) 9.(canceled)
 10. (canceled)
 11. (canceled)
 12. The content addressablememory of claim 1, wherein the capacitor has higher dielectric constantthan that of control circuit in the chip.
 13. The content addressablememory of claim 1, wherein the diode is formed from silicon diode. 14.The content addressable memory of claim 1, wherein the fourth terminalof the diode uses metal to form metal semiconductor diode.
 15. Thecontent addressable memory of claim 1, wherein the diode is formed fromcompound semiconductor diode, such as GaAs, SiGe.
 16. The contentaddressable memory of claim 1, wherein the diode is formed fromgermanium diode.
 17. (canceled)
 18. (canceled)
 19. (canceled)